1. Field of the Invention
The invention relates to a Multilayer circuit board used to mount, on a component such as a print-circuit board, an electronic part such as a semiconductor chip having connection electrodes arranged in the form of a lattice or a semiconductor device having external connection terminals arranged in the form of an area array.
2. Description of the Related Art
With recent semiconductor devices, logic devices are becoming highly functional and highly integrated, and the numbers of inputs and outputs have increased, resulting in a greatly increased mounting density. Accordingly, products which compensate for a lack of space for the formation of electrodes by arranging electrodes in a lattice pattern on the electrode-forming face of a semiconductor chip, have been provided.
FIG. 18 illustrates an example in which a semiconductor chip 4 is mounted on a circuit board 5 by conventional flip chip bonding. The semiconductor chip 4 has electrodes 6 arranged on the peripheral region thereof, the electrodes 6 being respectively connected to routing lines (wiring lines) 7 provided on the surface of the board 5.
FIG. 19 illustrates the arrangement of lands 8 and routing lines 7 provided on a circuit board for mounting a semiconductor chip (not shown). In this example, the lands 8 are arranged in two sequences corresponding to those of electrodes provided on the chip, the routing lines 7 from the lands 8 of the inner sequence being passed through between the adjacent lands 8 of the outer sequence. Thus, the respective routing lines 7 are routed out from the respective land 8 on the same plane (the surface of the circuit board).
When electrodes are arranged in more sequences on the electrode-forming face of a chip, however, it may no longer be possible to route out respective routing lines from respective lands on the same plane, depending upon the distance between the adjacent lands and the total number of lands.
To solve such a problem, a method has been proposed in which a circuit board for mounting a semiconductor chip is made so as to have a number of routing layers, each of the layers having patterned routing lines appropriately arranged thereon, to thereby connect some of electrodes of the chip with the respective routing lines. FIG. 20 schematically shows an example in which a semiconductor chip 4 provided with a number of electrodes 6 arranged in a lattice pattern is mounted on a multilayer circuit board 5xe2x80x2 comprising four routing layers 5a, 5b, 5c, and 5d. Using such a multilayer circuit board, it is possible to electrically connect the respective electrode 6 of the chip 4 with the respective routing lines 7a, 7b, 7c, 7d of the multilayer circuit board 5xe2x80x2, which are, in turn, connected with an external connection terminal 9 of the multilayer circuit board 5xe2x80x2, through which the chip 4 is ultimately electrically connected to an external electrical circuit of a component such as a printed circuit board (not shown).
When a semiconductor chip having a smaller number of electrodes arranged in a lattice pattern is to be mounted on a component, such as a printed circuit board, using a multilayer circuit board, it is sufficient that two or three routing layers are laminated to form the multilayer circuit board. However, if the semiconductor chip has as many as, for example 30xc3x9730 or 40xc3x9740 electrodes, much larger number, for example 6 to 10, of routing layers are required for the multilayer circuit board.
When a plurality of routing layers, on each of which patterned routing lines are densely formed, are to be laminated to provide a multilayer circuit board, a high-density routing method such as build-up method is employed. In the production of a multilayer circuit board by such a method, however, there are serious problems in terms of yield and reliability of the products, and the cost of production. Specifically, in the case of the production of the multilayer circuit board 5xe2x80x2 as illustrated in FIG. 20, the routing layers 5a, 5b, 5c, and 5d are successively laminated, while vias 3 are formed in each wiring layer 5a, 5b, 5c, 5d to secure an electric connection between the electrodes 6 of the chip 4 and the routing lines 7b, 7c, 7d on the routing layers 5b, 5c, 5d, or between the routing lines 7a, 7b, 7c, 7d on the layers 5a, 5b, 5c, 5d and the external connection terminals 9. Accordingly, the production process requires a high degree of precision, and does not necessarily provide higher reliability even at present. Also, in the case of the production of the multilayer circuit board, it is required that none of the layers to be laminated is defective, which increases in technical difficulty.
Consequently, to produce a reliable multilayer circuit board in a satisfactory yield, it would be very effective to reduce the number of routing layers.
The present invention relates to a multilayer circuit board for mounting thereon an electronic part such as a semiconductor chip or device having a large number of electrodes, for example as many as 40xc3x9740 electrodes, arranged in a certain pattern, such as a lattice pattern, on a side facing the multilayer circuit board, and aims to provide a multilayer circuit board product of high reliability, which has a reduced number of routing layers and can consequently be produced with an increased yield.
Thus, the invention provides a multilayer circuit board comprising a plurality of laminated routing layers, which is used to mount thereon an electronic part, such as a semiconductor chip or device, provided with electrodes formed in a certain pattern, each of the routing layers being provided with lands and routing lines on its surface, the lands being arranged to conform to the pattern of the electrodes of the electronic part, and the routing line being connected at its end to the land, and being routed toward the outside from a region where the lands are arranged, wherein the lands on each of the routing layers are arranged to have a pattern in which a closed virtual line formed by consecutively linking the peripheral lands at least partially has concave sections.
Preferably, the concave section is in the form of a rectangular equilateral triangle, and the peripheral lands are located along the sides of the rectangular equilateral triangle.
In some cases, the concave section may be in the form of a pseudo-rectangular equilateral triangle having a rectangular vertex at which one of the peripheral lands is located, and a cutout at an intersection of its hypotenuse and one of the equilaterals.